Principal Engineer, Analog Design (Team Lead) at Ambiq Micro — Singapore

<div class="content-intro">Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here.  </div>Scope  As Principal Engineer, Analog Design (Team Lead) at Ambiq, you will contribute to the technical roadmap and architecture for the company's core analog subsystems — including PMUs, clocking, and data converters — while directly leading and developing a team of analog designers.  This role sets technical direction across multiple concurrent programs, partners with Architecture, RTL, and Product teams at the roadmap level, and represents Ambiq's analog design capability to customers and partners. Designs span leading-edge technologies such as 22nm, 12nm, and beyond.  You will balance individual technical contribution with people leadership: driving the highest-risk architectural decisions personally while coaching Staff and Senior engineers through their own design cycles, spec definition, and career growth.  The successful candidate is a proven technical leader who elevates the people around them, sets a high bar for design rigor, and is comfortable being the final escalation point on the toughest analog design and organizational challenges.  This role will be onsite, and the candidate will be expected to have a presence on site 5 days a week.  Responsibilities  <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Own multi-generation architecture strategy and chip/block-level spec definition across analog subsystems </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Lead, mentor, and grow a team of analog design engineers, including hiring, career development, and performance management </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Set technical standards and design methodology for circuit architecture, verification, and layout supervision across the team </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Make final calls on the highest-risk circuit architecture and verification trade-offs </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Directly conduct or supervise transistor-level analog IC design for the most critical or novel circuit blocks </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Chair design reviews across multiple projects; drive resolution of the most complex action items </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Partner with digital design leadership to align interface specs and verification strategy for analog/digital integration </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Own the analog test and validation strategy for prototype bring-up through high-volume production </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Represent analog engineering in cross-functional roadmap, customer, and executive discussions </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Support Marketing, Product Engineering, and Applications leadership on product definition and customer commitments </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1">Drive continuous improvement in design flow, tools, and reuse strategy across the analog team </li> </ul>

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