Staff Engineer, Analog Layout at Ambiq Micro — Singapore

<div class="content-intro">Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here.  </div>Scope  As the Staff Engineer, Analog Layout at Ambiq, you will drive the physical implementation of key analog subsystems, including PMUs, clocking, and data converters, translating circuit architecture into silicon-ready layout that meets performance, area, matching, and reliability targets.  This role works closely with Analog Design and RTL/Physical Design teams to implement custom analog layouts that meet and exceed customer needs. Designs will be in leading-edge technologies, such as 22nm, 12nm, and beyond.  The successful candidate will be a highly motivated team player who, through collaboration with designers and layout peers, will help everyone succeed.  The person in this role will be well-rounded, having been through a number of design cycles. They will have layout-related experience across the full flow, from floorplanning and whiteboarding with designers, to detailed layout and parasitic extraction, to LVS/DRC closure and tape-out, through validation and production test support.  This role will be onsite, and the candidate will be expected to have a presence on site 5 days a week.  Responsibilities  <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Partner with analog designers on chip-level and block-level floorplanning and layout strategy </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Lead layout for complex blocks and closely supervise or review layout work from other layout engineers </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Conduct layout design reviews and resolve action items generated as a result of these reviews </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Attend circuit design reviews to provide layout feasibility input and guidance to designers and other layout engineers </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Work with analog and digital designers to ensure layout meets circuit intent and interface requirements </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Support prototype chip bring-up and testing to help validate analog circuit blocks against layout-dependent effects </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Support development of manufacturing test plans where layout impacts testability (e.g., probe access, trim structures) </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1">Support Product Engineering to meet manufacturing/production needs related to layout and yield </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":450,"335559991":270,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="12" data-aria-level="1">Support Applications Engineering on layout-related customer questions (e.g., matching, noise, reliability) </li> </ul>

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