Design Verification Engineer, Hardware

<p>At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.</p> <h3>Who we are</h3> <p>We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.</p> <h3>About the Role</h3> <p>We are seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc). You will collaborate with RTL design, performance modeling and verification, and compiler teams.</p> <h3>What You’ll Do</h3> <ul> <li><strong>Verification Strategy &amp; Planning:</strong> Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.</li> <li><strong>UVM Environment Development:</strong> Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM (Universal Verification Methodology).</li> <li><strong>Constrained-Random Testing:</strong> Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.</li> <li><strong>Coverage-Driven Verification:</strong> Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.</li> <li><strong>Formal Verification:</strong> Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove the correctness of critical logic.</li> <li><strong>Emulation</strong>: Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.</li> <li><strong>Debug &amp; Analysis:</strong> Debug failures using waveform viewers and work closely with RTL designers to resolve functional bugs and architectural non-compliance.</li> <li><strong>Automation &amp; Scripting:</strong> Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.</li> </ul> <h3>Skills and Qualification</h3> <p><strong>Minimum Qualifications:</strong></p> <ul> <li>Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.</li> <li>Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).</li> <li>Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.</li> <li>Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).</li> <li>Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).</li> <li>A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.</li> </ul> <p><strong>Preferred Qualifications: (We encourage you to apply even if you don’t meet all of these)</strong></p> <ul> <li>Proficiency SystemVerilog Assertions (SVA) and formal tools (&nbsp;Jasper, VC Formal) to catch temporal logic bugs at the source.</li> <li>Understanding of emulation and prototyping solutions and test environments.</li> <li>Hands-on experience in post-Silicon bringup, testing, and debug.</li> <li>Experience in workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.</li> </ul> <p><strong>Logistics &amp; Benefits</strong></p> <ul> <li><strong>Location:</strong> This role is based in <strong>Austin, Texas or</strong> <strong>Palo Alto, California.</strong></li> <li><strong>Compensation:</strong> Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.</li> <li><strong>Visa Sponsorship:</strong> We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.</li> <li><strong>Benefits:</strong> River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.</li> </ul> <p>&nbsp;</p>