Physical Design Engineer, Hardware

<p>At River, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.</p> <h3>Who we are</h3> <p>We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.</p> <h3>About the Role</h3> <p>We are looking for exceptional physical design engineers to transform our high-performance architectural concepts into production-ready silicon. You will own the physical implementation flow from synthesis through tape-out, pushing the absolute limits of advanced foundry nodes to maximize PPA. You will take ownership of block-level and top-level physical design, collaborating tightly with RTL designers to close timing, electrical, and physical verification for our custom AI accelerator.</p> <h3>What You’ll Do</h3> <ul> <li><strong>Drive Synthesis and Place-and-Route:</strong>&nbsp;Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis (CTS), and routing for high-performance blocks.</li> <li><strong>Maximize PPA:</strong> Optimize layout topologies to maximize cell density and utilization, architecting robust power delivery networks (PDN) to minimize IR drop and meet aggressive frequency targets on advanced foundry nodes.</li> <li><strong>Close Timing &amp; Electricals:</strong>&nbsp;Conduct static timing analysis (STA), fix setup/hold violations across complex clock domains, and resolve signal integrity (SI), electromigration (EM) and IR-drop constraints.</li> <li><strong>Execute Physical Verification:</strong>&nbsp;Run and debug sign-off physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Antenna rule compliance.</li> <li><strong>Co-Design with RTL:</strong> Partner directly with the RTL team to provide early physical feedback on logic structures, pipeline depth, and routing congestion to streamline implementation closure.</li> <li><strong>Advance Flow Automation:</strong> Integrate and develop next-generation AI-driven EDA tools and workflows to fundamentally accelerate the physical implementation cycle and optimize design closure.</li> </ul> <h3>Skills and Qualifications</h3> <p><strong>Minimum Qualifications:</strong></p> <ul> <li>Bachelor’s degree in Electrical Engineering or Computer Engineering, and 5+ years practical industry experience working with advanced process nodes (7nm or below).</li> <li>Deep hands-on proficiency with industry-standard physical design, timing, and sign-off tools (e.g., Innovus, Fusion Compiler, PrimeTime, RedHawk).</li> <li>Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using power intent specifications (UPF/CPF).</li> <li>Exceptional debugging skills with a first-principles approach to navigating complex trade-offs between congestion, timing slack, and power density in highly utilized designs.</li> <li>A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with RTL and architecture teams.</li> </ul> <p><strong>Preferred Qualifications: (We encourage you to apply even if you don't meet all of these)</strong></p> <ul> <li>An extensive track record of delivering high-performance SoCs, CPUs, GPUs, or AI accelerators through multiple successful production tape-outs.</li> <li>Hands-on experience optimizing physical layouts for highly parallel compute structures, such as systolic arrays, large tensor execution units, or high-bandwidth memory (HBM) interfaces.</li> <li>Experience custom-scripting or extending EDA tools (using Tcl, Python, or specialized ML APIs) to automate physical design closure and build bespoke workflow pipelines.</li> </ul> <h3>Logistics</h3> <ul> <li><strong>Location:</strong> This role is based in <strong>Austin, Texas or</strong> <strong>Palo Alto, California.</strong></li> <li><strong>Compensation:</strong> Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.</li> <li><strong>Visa Sponsorship:</strong>&nbsp;We sponsor visas and are committed to supporting the process for the right candidate.</li> <li><strong>Benefits:</strong> River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.</li> </ul> <p>&nbsp;</p>