We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization.   Core Responsibilities: <ul> <li>Develop and optimize flip chip attach processes including bump formation,</li> </ul> placement, reflow, and underfill for high-performance semiconductor packages. <ul> <li>Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps)</li> </ul> and substrate pad finishes for robust interconnect performance. <ul> <li>Drive package integration from die to substrate, ensuring alignment, coplanarity,</li> </ul> and yield optimization. <ul> <li>Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding,</li> </ul> head-in-pillow, and interconnect defects. <ul> <li>Collaborate with substrate vendors, OSATs, and internal teams to define design</li> </ul> rules (pad pitch, bump pitch, keep-outs, stack-ups). <ul> <li>Lead process development for reflow profiles, flux selection, cleaning, and underfill</li> </ul> dispense/cure. <ul> <li>Perform root cause analysis of assembly and reliability failures using cross-</li> </ul> sectioning, SEM, CSAM, and other failure analysis techniques. <ul> <li>Support reliability qualification including thermal cycling, drop, mechanical shock,</li> </ul> and power cycling. <ul> <li>Work cross-functionally with design, reliability, thermal, and manufacturing teams</li> </ul> to ensure robust package performance from concept through high-volume production.     Required Technical Skills: <ul> <li>Strong experience in flip chip packaging and assembly processes for</li> </ul> semiconductor devices. <ul> <li>Deep understanding of bumping technologies (solder bumps, Cu pillar, micro-</li> </ul> bumps) and UBM/metallization systems. <ul> <li>Experience with underfill materials, dispense techniques, flow behavior, and cure</li> </ul> processes. <ul> <li>Understanding of thermo-mechanical behavior in flip chip assemblies (CTE</li> </ul> mismatch, warpage, solder fatigue, reliability risks). <ul> <li>Hands-on experience with failure analysis and reliability testing (cross-sections,</li> </ul> SEM, CSAM, thermal cycling). <ul> <li>Ability to work with OSATs and suppliers to develop and transfer assembly</li> </ul> processes into production. <ul> <li>Strong problem-solving skills with ability to debug yield and reliability issues in</li> </ul> manufacturing environments.     Preferred / Differentiating Skills: <ul> <li>Experience with III-V packaging, photonics packaging, and precision chip attach.</li> <li>Experience with advanced packaging technologies including 2.5D interposers, 3D</li> </ul> stacking, chiplets, and CoWoS-like architectures. <ul> <li>Familiarity with bill of materials used in photonics packaging such as clear</li> </ul> adhesives and underfills as well as mold compounds and underfills for 2.5D advanced packaging. <ul> <li>Familiarity with fine-pitch micro-bump and hybrid bonding approaches.</li> <li>Experience integrating high-power or high-TDP devices with tight warpage and</li> </ul> thermal constraints. <ul> <li>Exposure to thermo-mechanical modeling or collaboration with simulation teams</li> </ul> for warpage and reliability prediction. <ul> <li>Understanding of system-level interactions (PCB attach, second-level interconnect</li> </ul> reliability).

Packaging Engineer- Flip Chip

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