XPU Architect

<p><strong>What We’re Looking For:</strong></p> <p>&nbsp;</p> <p>We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs.&nbsp;</p> <p>&nbsp;</p> <p><strong>Ideal Background:</strong></p> <p>&nbsp;</p> <p>An ideal candidate will have:</p> <ul> <li>Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar)&nbsp;</li> <li>Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options</li> <li>Deep understanding of AI workloads, especially low latency LLM inference&nbsp;</li> <li>Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc.&nbsp;</li> </ul> <p><br><br><br></p> <p><strong>Strongly Preferred:</strong></p> <p>&nbsp;</p> <ul> <li>Hands-on experience with AI chip architecture and tapeouts&nbsp;</li> <li>End to end ownership of at least one AI ASIC project&nbsp;</li> <li>History of product delivery (regardless of ultimate commercial success of said product)&nbsp;</li> <li>Experience with HBM-based AI chip architecture&nbsp;</li> <li>Experience in proposing “weird” chip architectures (in any domain, not just AI!)</li> </ul>